Piezoresistance—the effect of mechanical changes on resistance—is currently used to improve the performance of silicon-based electronic devices. Several recent publications have reported an effect called giant piezoresistance in silicon nanowires: an applied mechanical stress appears to change the wire’s resistance by an amount that is orders of magnitude greater than what is found in bulk silicon. For understandable reasons, this is intriguing to scientists and engineers working in areas ranging from nanoelectromechanical systems (NEMS) to biosensors.
Now, in their article in Physical Review Letters, Jason Milne and Alistair Rowe at Ecole Polytechnique and Steve Arscott at the Institute d’Electronique, de Microélectronique et de Nanotechnologie, both in France, and Christoph Renner at the University of Geneva, Switzerland, present evidence suggesting that the reported giant piezoresistance may have been an artifact.
Working with various silicon nano- and microstructures, the authors show that electrons and holes trapped at the surface, and not mechanical stress, are responsible for the large swings in resistance. In effect, the very act of measuring the resistance changes its value. The new work indicates that the magnitude of piezoresistance in wires is really no different from that in bulk silicon. Moreover, the charge trapping (or, “dielectric relaxation”) that occurs at the surface both swamps the true piezoresistance and results in apparent giant piezoresistance signatures that are identical to what was reported earlier. While Milne et al.’s results may not quite mean a back-to-the-drawing-board scenario, it points to the importance of making sure—in future experiments—that applied stress alone is causing the changes in resistance in these structures. – Sami Mitra